1. Field of the Invention
This invention generally relates to data processing, and more specifically, to isolating input/output adapter addressing domains in a data processing system. Even more specifically, the invention relates to isolating input/output adapter addressing domains in a logically partitioned data processing system operating in a HyperTransport environment.
2. Background Art
In an LPAR data processing system, multiple operating systems or multiple copies of a single operating system are run on a single data processing system platform. Each operating system or operating system copy executing within the data processing system is assigned to a different logical partition, and each partition is allocated a non-overlapping subset of the resources of the platform. Thus, each operating system or operating system copy directly controls a distinct set of allocatable resources within the platform.
Among the platform resources that may be allocated to different partitions in an LPAR data processing system include processors or time slices of processors, regions of system memory and IOAs or parts of IOAs. Thus, different regions of system memory and different IOAs or parts of IOAs may be assigned to different partitions of the system. In such an environment, it is important that the platform provide a mechanism to enable IOAs or parts of IOAs to obtain access to all the physical memory that they require to properly service the partition or partitions to which they have been assigned; while, at the same time prevent IOAs or parts of IOAs from obtaining access to physical memory that has not been allocated to their associated partitions.
In a LPAR data processing system, various communication technologies may be used to link together the electronic devices of the system via both physical media and wirelessly. Some communication technologies interface a pair of devices, other communication technologies interface small groups of devices, and still other communication technologies interface large groups of devices.
One relatively new communication technology for coupling relatively small groups of devices is the HyperTransport (HT) technology. The HT Standard sets forth definitions for a high-speed, low-latency protocol that can interface with today's buses like AGP, PCI, SPI, 1394, USB 2.0, and IGbit Ethernet as well as next generation buses including AGP 8x, Infiniband, PCI-X, PCI 3.0, PCIe, and 10 Gbit Ethernet. HT interconnects provide high-speed data links between coupled devices. Most HT enabled devices include at least a pair of HT ports so that HT enabled devices may be daisy-chained. In an HT chain or fabric, each coupled device may communicate with each other coupled device using appropriate addressing and control. Examples of devices that may be HT chained include packet data routers, server computers, data storage devices, and other computer peripheral devices, among others.
HT thus offers many important advantages. Using HyperTransport attached I/O bridges in a logically partitioned data processing system, however, requires a way of isolating I/O adapter DMA and interrupt requests to the owning LPAR.
Importantly, one LPAR could affect another through an IOA. With LPAR, the OS does not guarantee successful communications. For example, one OS may send commands and addresses to an IOA, and the IOA would do the DMA using these addresses. There is no mechanism to check the addresses provided by the OS to the IOA. Instead, the BAR/limit (and later, the TVT structure) verifies the address when it is presented to the host by the IOA.